1. Field of the Invention
The present invention relates, in general, to a semiconductor device and, more particularly, to a semiconductor device reduced in connecting area in which a drain electrode of PMOS is connected with a drain electrode of NMOS, and a method for fabrication thereof.
2. Description of the Prior Art
High integration of a semiconductor device is accomplished with a great diminution in the area occupied by a unit cell. An area in a semiconductor device for interconnecting a drain of PMOS with a drain of NMOS is generally known to be the structure which occupies the largest area in a semiconductor device. This interconnection is typically accomplished through a contact hole with a conductive wire.
In order to better understand the background of the present invention, the conventional techniques for fabrication of a semiconductor device will be described with reference to some drawings.
FIG. 1 is a circuit diagram showing a semiconductor device widely used in an integrated circuit. As shown in this figure, V.sub.DD is connected with a source electrode of PMOS; a drain electrode of PMOS with a drain electrode of NMOS; a source electrode of NMOS with V.sub.SS. In this circuit diagram, depending upon the voltage applied to the gate electrode (V.sub.in) of PMOS or NMOS, the output voltage (V.sub.out) of PMOS or NMOS is determined.
FIG. 2 shows a semiconductor device of FIG. 1 fabricated on a semiconductor substrate in a conventional technique. As shown in this figure, a semiconductor substrate 1 is provided with an N-well 10 and a P-well 20. An element isolation insulating layer 2 is formed on the boundary between the N-well 10 and the P-well 20. Then, a PMOS transistor consisting of a gate oxide 3, a gate electrode 4, a source electrode 15A, and a drain electrode 15B is fabricated on an active region of the N-well 10. Likewise, an NMOS transistor consisting of a gate oxide 3, a gate electrode 4, a source electrode 25A, and a drain electrode 25B is fabricated on an active region of the P-well 20. Thereafter, a blanket insulating layer is deposited over the resulting structure. Two contact holes are formed exposing the drain electrode 15B of PMOS and the drain electrode 25B of NMOS, respectively. In order to interconnect the drain electrode 15B of PMOS With the drain electrode 25B of NMOS, a conductive wire is formed filling the two contact holes.
However, although such prior art techniques, that is, the element isolation layer between the N-well and the P-well and the contact holes exposing the drain electrodes of the PMOS and NMOS, can reduce the size of a semiconductor device to some degree, it is virtually impossible to achieve a very high integration of a semiconductor device through such prior art techniques.